Method of using materials based on Ruthenium and Iridium and their oxides, as a Cu diffusion barrier, and integrated circuits incorporating same

ABSTRACT

The present invention generally relates to methods used for fabricating integrated circuits (“ICs”), using Ruthenium (“Ru”) and its oxides and/or Iridium (“Ir”) and its oxides as the diffusion barrier to contain and control copper (“Cu”) interconnects. The invention also covers ICs incorporating such materials in the diffusion barrier to contain and control the Cu interconnects. The present invention advantageously provides better integration and fabrication of advanced IC chips with sub-micron features.

CROSS REFERENCE TO RELATED APPLICATION

[0001] This application is related to U.S. provisional patentapplication No. 60/393,204, filed Jul. 2, 2002, entitled “METHOD OFUSING MATERIALS BASED ON RUTHENIUM AND IRIDIUM AND THEIR OXIDES, AS A CuDIFFUSION BARRIER, AND INTEGRATED CIRCUITS INCORPORATING SAME”, theentire contents of which are incorporated herein by this reference. TheApplicants hereby claim the benefits of this earlier pending provisionalapplication under 35 U.S.C. Section 119(e).

TECHNICAL FIELD OF THE INVENTION

[0002] This invention generally relates to methods used for fabricatingintegrated circuits (“ICs”), specifically methods of using certainmaterials as the diffusion barrier to contain copper (“Cu”)interconnects. The invention also covers ICs incorporating suchmaterials in the diffusion barrier to contain the Cu interconnects. Thepresent invention advantageously provides better integration andfabrication of advanced IC chips with sub-micron features.

BACKGROUND OF THE INVENTION

[0003] In the sub-100 nm generation of integrated circuits (“ICs”), itis anticipated that copper (“Cu”) will replace aluminum as the newinterconnect material due to its favorable electrical conductivity (1.67μΩ.cm vs. 2.66 μΩ.cm of aluminum) and its superior resistance toelectromigration. Additionally, improved electromigration resistanceallows integrated circuits to operate at higher current densities andpossibly at higher temperatures. IC chips fabricated with moreconductive Cu interconnects and low-k dielectrics operate with lesspower and at significantly higher speed due to decreases in theinterconnect RC coupling delay. The new dual-damascene patterningprocess coupling with chemical-mechanical planarization (CMP)significantly simplifies Cu interconnect routing and lowersmanufacturing costs.

[0004] However, copper diffuses easily into active silicon devices andinterlayer dielectrics (“ILD”), especially under electrical and thermalstresses resulting in deep level traps in the Si band gap. To preventcatastrophic contamination caused by Cu diffusion, diffusion barrierslike tantalum (“Ta”) and tantalum nitride (“TaN”) are currentlydeposited in the damascene trench/via features by physical vapordeposition (PVD) to contain Cu interconnects. Since thin barrier layersof Ta (13.2 μΩ.cm) and TaN (>200 μΩ.cm) are too resistive to plate Cudirectly, a continuous Cu-seeding layer (>7.5 nm) must be deposited overthe Ta/TaN barrier to assure a good Cu electrofill.

[0005] The most challenging aspect of implementing Cu interconnects foradvanced complementary metal-oxide-semiconductor (“CMOS”) applicationsbeyond the 100 nm mode is the increasing difficulty with the overallprocess integration. Shrinking dimensions demand an increasinglyhigh-aspect-ratio of trench/via features that make PVD barrier/seeddeposition and Cu electrofill more difficult. The space situation ismost severe at the bottom metallization layer where the firstconnections to sub-100 nm transistor array are made. For the future45-65 nm CMOS devices, the thickness of a functional diffusion barrieris limited to merely 5 nm at this crucial metal layer. The currentCu/Ta/TaN stack approach can not be scaled down to meet the futureindustry roadmap requirements. In addition, any discontinuities in theCu seed layer, large overhang, or poor coverage on the lower sidewallcan affect the Cu electroplating through an early pinch-off of thestructure, resulting in a void defect being formed. Structural integrityconcerns and adhesion issues of the barrier metal to the new ultra low-kdielectric are often mentioned as accompanying problems.

[0006] The present invention greatly reduces the overall integrationdifficulties by replacing the current Cu Seed/Ta/TaN trilayer barrierconfiguration with a directly Cu-plate-able barrier layer consisting ofa combination of Ruthenium (“Ru”) and Iridium (“Ir”) and theirconductive oxides Ruthenium Oxide (“RuO₂”) and Iridium Oxide (“IrO₂”).The exact lateral chemical composition of this novel (Ru, RuO₂) and/or(Ir, IrO₂) diffusion barrier can be fine tuned to achieve strongadhesion between Cu/(Ru, RuO₂)/interlayer dielectrics. With the newdirectly Cu-plate-able diffusion barrier, the costly Cu-seed layer canbe eliminated which will greatly decrease copper interconnect processingcosts and further simplifying circuit design and promoting overallintegration success.

BRIEF SUMMARY OF THE INVENTION

[0007] The present invention utilizes a novel directly Cu-plate-ablediffusion barrier consisting of conductive Ru and/or RuO₂ and Ir and/orIrO₂ and their combinations, in single or multi-layers, to eliminate theadditional Cu-seeding layer and provide strong interlayer adhesionbetween Cu/diffusion barrier/interlayer dielectrics. The presentinvention encompasses ICs made with said barrier materials.

DESCRIPTION OF THE PRIOR ART

[0008] In U.S. Pat. No. 6,441,492 to Cunningham, disclosure is made ofan IC with a barrier layer preferably comprising at least one ofrhodium, ruthenium or rhenium. However, Cunningham does not disclose orclaim said element being applied in an atomic layer deposition processor in combination with Ir and its conductive oxide, and its superiorinterlayer adhesion characteristics, based on the Ru and/or RuO₂ and Irand/or IrO₂ multi-layer composition.

DESCRIPTION OF THE DRAWINGS

[0009]FIG. 1 illustrates the conventional use of Ta and TaN as a barriermaterial;

[0010]FIG. 2 illustrates the deposition of Ru/RuO₂, and it's use as abarrier material according to the present invention;

[0011]FIG. 3 is a graph illustrating the X-ray diffraction pattern ofthe Ru substrate;

[0012]FIG. 4 is a graph illustrating the X-ray diffraction patternbetween the Cu deposit and the Ru substrate at 25 degrees Celsius;

[0013]FIG. 5 is a graph illustrating the X-ray diffraction patternbetween the Cu deposit and the Ru substrate at 800 degrees Celsius;

[0014]FIG. 6 is a graph illustrating the electroplating of Cu on the Rusubstrate;

[0015]FIG. 7 illustrates the use of Ir/IrO₂ as a barrier materialaccording to the present invention;

[0016]FIG. 8 is a graph illustrating the X-ray diffraction pattern ofthe Ir substrate;

[0017]FIG. 9 is a graph illustrating the X-ray diffraction patternbetween the Cu deposit and the Ir substrate at 25 degrees Celsius;

[0018]FIG. 10 is a graph illustrating the X-ray diffraction patternbetween the Cu deposit and the Ir substrate at 600 degrees Celsius;

[0019]FIG. 11 is a graph illustrating the electroplating of the Cu onthe Ir substrate.

[0020]FIG. 12 is an optical image of an electroplated Cu film depositedon a (Ru, RuO2) barrier deposited on SiO₂ coated wafer after 500° C.annealing.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

[0021] Ideal diffusion barriers should have good adhesion to both copperand interlayer dielectrics, in addition to affording a conductive Cuplating platform that is utilized for the bottom-up Cu electrofill ofdamascene features. FIG. 1 illustrates the conventional use of Ta andTaN as a barrier material in a portion of IC 10. As can be seen therein,the Cu electrofill 11 is separated from the interlevel dielectric(“ILD”) 14 by the Cu seed layer 11, the Ta layer 12 and a TaN layer 13.

[0022] The present invention is an improvement over the conventionalart. The present invention employs a Ru, and/or RuO₂ and Ir, and/or IrO₂combination diffusion barrier material to replace the more resistiveTa/TaN barrier and eliminate the need for an additional costly Cu-seedlayer. Ru is an air-stable transition metal of high melting point (2310°C.) that has nearly twice the electrical conductivity (7.6 μΩ.cm) andthermal conductivity as Ta. Furthermore, Ru, like Ta, shows negligiblesolid solubility with Cu up to 900° C. based on the binary phase diagramand is therefore a good barrier candidate. Cu plates easily and exhibitsexcellent adhesion on Ru substrates. More importantly, as seen in FIGS.3 to 5, X-ray diffraction (“XRD”) patterns indicate no new phases orintermetallic compound formation between the Cu deposit and Ru substrateeven after annealing at 800° C. The observed chemical stability of theCu/Ru interface under high thermal stress underscores the potential ofRu as an effective Cu diffusion barrier.

[0023]FIGS. 2 and 7 illustrate the use of more conductive barriermaterials to replace Ta and TaN, according to the present invention. Thebarrier materials can be Ru and RuO₂ alone or in combination, Ir andIrO₂, alone or in combination, or the four in combination. As can beseen in FIG. 2, the Cu electrofill 21 is separated from the ILD 23 onlyby the Ru/RuO₂ combination layer 22. The use of these materialsadvantageously permits direct Cu electrofill without the need of anadditional Cu seed layer. This advantageously provides betterintegration of the Cu in advanced IC chips with sub-micron features. Notshown in the Figure but within the scope of the present invention is theuse of the barrier materials Ru/RuO₂ and Ir/IrO₂ in combination.

[0024] A strong adhesion between Cu/barrier/ILD is most critical if thefabricated Cu interconnect microstructures are to have sufficientmechanical strength to withstand the demanding chemical-mechanicalplanarization process currently used in IC fabrication. The presentinvention uses Ru/RuO₂ and Ir/irO₂, each alone or in combination, toachieve the stringent adhesion requirement. Cu adheres strongly on Ru,RuO₂, Ir and IrO₂ surfaces. More importantly, RuO₂ and IrO₂ can functionas an adhesion layer to secure a Ru and/or RuO₂ and Ir, and/or IrO₂barrier on various ILD materials. FIG. 12 demonstrates the excellentadhesion, confirmed by scribe and peel test, between Cu/(Ru, RuO₂)/SiO₂even after annealing at 500° C. The present invention allows flexibilityin fine adjusting (Ru, RuO₂) and (Ir, IrO₂) composite layer in thebarrier design to achieve the optimum integration success.

[0025] Metal inter-diffusion will occur if mixing leads to a lowering ofthe free energy of interface. In a thin non-epitaxial metal film, grainboundaries and dislocations are abundant and, as a result, Cu diffusionthrough grain boundaries and dislocations are dominant, especially ifthe diffusion temperatures are low. In contrast to the resistive TaNbarrier, RuO₂ and IrO₂ have a metal-like conductivity resulting from apartial filling of the metal and oxygen electronic band structure. Thepresent invention utilizes the conductive RuO₂ and IrO₂ as “diffusionstuffers” to prevent the grain boundary diffusion of Cu into thenanometer scale Ru and Ir barrier layer. Oxygen impurities/stuffers aredelivered to the more energetic grain boundaries and dislocations on theRu surface by electrochemical, thermal oxidation, atomic layerdeposition, and physical vapor deposition. Again, the relative locationof RuO₂ and IrO₂ as “diffusion stuffers” can be freely adjust within the(Ru, RuO₂) and (Ir, IrO₂) composite layer in the barrier design toachieve the optimum integration success.

[0026]FIG. 3 is a graph illustrating the X-ray diffraction pattern ofthe Ru substrate before Cu is deposited.

[0027]FIG. 4 is a graph illustrating the X-ray diffraction patternbetween the Cu electrofill deposit and the Ru substrate at 25 degreesCelsius. As seen therein, no new phases or intermetallic compoundformation occurs between the Cu deposit and Ru substrate.

[0028] Further, as can be seen in FIG. 5, which is also a graphillustrating the X-ray diffraction pattern between the Cu deposit andthe Ru substrate, no new phases or intermetallic compound formationoccurs between the Cu deposit and Ru substrate even after annealing at800° degrees Celsius. The chemical stability of the Cu/Ru interfaceunder high thermal stress illustrates the advantages of Ru as aneffective Cu diffusion barrier.

[0029] The X-ray diffusion data as shown in FIGS. 3, 4 and 5 also revealfavorable heteroepitaxial growth of Cu by electroplating on Ru withstrong Cu(111) texture. Enhanced Cu(111) texture advantageously reducesdefects at the interface and improves the electromigration reliabilityof the Cu interconnects

[0030] As can be seen in FIG. 6, the Cu plates easily to the Rusubstrate and exhibits excellent adhesion thereon by a separate 3M tapetest. Specifically, the adhesion was tested after the electroplating ofthe Cu on the Ru substrate from an acid sulfate bath. The plating bathcomprised CUSO₄, and/or H₂SO₄. The plating techniques comprised linearsweep voltammetry and or Tungsten potential stepping. The platingefficiency was greater than 80% and the electrode configurationcomprised an Ru disk or Ru coated silicon wafer working electrode withappropriate reference and counter electrodes.

[0031] As can be seen in FIG. 7, the Cu electrofill 71 is separated fromthe ILD 73 only by the Ir/IrO₂ combination layer 72. The use of thesematerials advantageously permits direct Cu electrofill without the needof an additional Cu seed layer. This advantageously provides betterintegration of the Cu in advanced IC chips with sub-micron features.

[0032]FIG. 8 is a graph illustrating the X-ray diffraction pattern ofthe Ir substrate before the Cu is deposited.

[0033]FIG. 9 is a graph illustrating the X-ray diffraction patternbetween the Cu electrofill deposit and the Ir substrate at 25 degreesCelsius. As seen therein, no new phases or intermetallic compoundformation occurs between the Cu deposit and Ir substrate.

[0034] Further, as can be seen in FIG. 10, which is also a graphillustrating the X-ray diffraction pattern between the Cu deposit andthe Ir substrate, no new phases or intermetallic compound formationoccurs between the Cu deposit and Ir substrate even after annealing at600° degrees Celsius. The chemical stability of the Cu/Ir interfaceunder high thermal stress illustrates the advantages of Ir as aneffective Cu diffusion barrier.

[0035] The X-ray diffusion data as shown in FIGS. 8, 9 and 10 alsoreveal favorable heteroepitaxial growth of Cu by electroplating on Irwith strong Cu(111) texture. Enhanced Cu(111) texture advantageouslyreduces defects at the interface and improves the electromigrationreliability of the Cu interconnects.

[0036] As can be seen in FIG. 11, the Cu plates easily to the Irsubstrate and also exhibits excellent adhesion thereon by a separate 3Mtape test. Specifically, the adhesion was tested after theelectroplating of the Cu on the Ir substrate from an acid sulfate bath.

[0037]FIG. 12 is an optical image of an electroplated Cu film depositedon a (Ru, RuO2) barrier deposited on SiO₂ coated wafer after 500° C.annealing. As can be seen, the Cu film remains intact along the edges ofdeep gouges after peel test by scotch tape clearly demonstrating theexcellent adhesion between the plated Cu and (Ru, RuO2).

[0038] The innovative teachings of the present invention are describedwith particular reference to the disclosed embodiments. However, itshould be understood that these embodiments provide only two examples ofthe many advantageous uses and innovative teachings herein. Variousalterations, modifications and substitutions can be made to thedisclosed invention without departing in any way from the spirit andscope of the invention. The invention covers ICs for use in any deviceor apparatus which is made with the materials described herein as adiffusion barrier.

What is claimed is:
 1. A method of controlling and containing copperdiffusion during the integration of copper interconnects during thefabrication of integrated circuits, comprising: preparing an inter-leveldielectric substrate; depositing a layer of Ru on the inter-leveldielectric substrate; depositing a layer of RuO₂ as a diffusion stufferon the Ru layer; and depositing copper on the RuO₂ layer.
 2. The methodof controlling and containing copper diffusion during the integration ofcopper interconnects during the fabrication of integrated circuits ofclaim 1, further comprising depositing multiple layers of Ru and RuO₂between the inter-level dielectric substrate and the copper layer. 3.The method of controlling and containing copper diffusion during theintegration of copper interconnects during the fabrication of integratedcircuits of claim 2, further comprising depositing the RuO₂ layer(s) onthe Ru layer(s) using an atomic layer deposition technique.
 4. Themethod of controlling and containing copper diffusion during theintegration of copper interconnects during the fabrication of integratedcircuits of claim 2, further comprising depositing the RuO₂ layer(s) onthe Ru layer(s) using a thermal oxidation technique.
 5. The method ofcontrolling and containing copper diffusion during the integration ofcopper interconnects during the fabrication of integrated circuits ofclaim 2, further comprising depositing the RuO₂ layer(s) on the Rulayer(s) using an electrochemical technique.
 6. The method ofcontrolling and containing copper diffusion during the integration ofcopper interconnects during the fabrication of integrated circuits ofclaim 2, further comprising depositing the RuO₂ layer(s) on the Rulayer(s) using physical vapor deposition.
 7. The method of controllingand containing copper diffusion during the integration of copperinterconnects during the fabrication of integrated circuits of claim 1,further comprising depositing the RuO₂ layer on the Ru layer using anatomic layer deposition technique.
 8. The method of controlling andcontaining copper diffusion during the integration of copperinterconnects during the fabrication of integrated circuits of claim 1,further comprising depositing the RuO₂ layer on the Ru layer using athermal oxidation technique.
 9. The method of controlling and containingcopper diffusion during the integration of copper interconnects duringthe fabrication of integrated circuits of claim 1, further comprisingdepositing the RuO₂ layer on the Ru layer using an electrochemicaltechnique.
 10. The method of controlling and containing copper diffusionduring the integration of copper interconnects during the fabrication ofintegrated circuits of claim 1, further comprising depositing the RuO₂layer on the Ru layer using physical vapor deposition.
 11. A method ofcontrolling and containing copper diffusion during the integration ofcopper interconnects during the fabrication of integrated circuits,comprising: preparing an inter-level dielectric substrate; depositing alayer of Ir on the inter-level dielectric substrate; depositing a layerof IrO₂ as a diffusion stuffer on the Ir layer; and depositing copper onthe IrO₂ layer.
 12. The method of controlling and containing copperdiffusion during the integration of copper interconnects during thefabrication of integrated circuits of claim 11, further comprisingdepositing multiple layers of Ir and IrO₂ between the inter-leveldielectric substrate and the copper layer.
 13. The method of controllingand containing copper diffusion during the integration of copperinterconnects during the fabrication of integrated circuits of claim 12,further comprising depositing the IrO₂ layer(s) on the Ir layer(s) usingan atomic layer deposition technique.
 14. The method of controlling andcontaining copper diffusion during the integration of copperinterconnects during the fabrication of integrated circuits of claim 12,further comprising depositing the IrO₂ layer(s) on the Ir layer(s) usinga thermal oxidation technique.
 15. The method of controlling andcontaining copper diffusion during the integration of copperinterconnects during the fabrication of integrated circuits of claim 12,further comprising depositing the IrO₂ layer(s) on the Ir layer(s) usingan electrochemical technique.
 16. The method of controlling andcontaining copper diffusion during the integration of copperinterconnects during the fabrication of integrated circuits of claim 12,further comprising depositing the IrO₂ layer(s) on the Ir layer(s) usingphysical vapor deposition.
 17. The method of controlling and containingcopper diffusion during the integration of copper interconnects duringthe fabrication of integrated circuits of claim 11, further comprisingdepositing the IrO₂ layer on the Ir layer using an atomic layerdeposition technique.
 18. The method of controlling and containingcopper diffusion during the integration of copper interconnects duringthe fabrication of integrated circuits of claim 11, further comprisingdepositing the IrO₂ layer on the Ir layer using a thermal oxidationtechnique.
 19. The method of controlling and containing copper diffusionduring the integration of copper interconnects during the fabrication ofintegrated circuits of claim 11, further comprising depositing the IrO₂layer on the Ir layer using an electrochemical technique.
 20. The methodof controlling and containing copper diffusion during the integration ofcopper interconnects during the fabrication of integrated circuits ofclaim 11, further comprising depositing the IrO₂ layer on the Ir layerusing physical vapor deposition.
 21. A method of controlling andcontaining copper diffusion during the integration of copperinterconnects during the fabrication of integrated circuits, comprising:preparing an inter-level dielectric substrate; depositing a layer of Iron the inter-level dielectric substrate; depositing a layer of RuO₂ as adiffusion stuffer on the Ir layer; and depositing copper on the RuO₂layer.
 22. The method of controlling and containing copper diffusionduring the integration of copper interconnects during the fabrication ofintegrated circuits of claim 21, further comprising depositing multiplelayers of Ir and RuO₂ between the inter-level dielectric substrate andthe copper layer.
 23. A method of controlling and containing copperdiffusion during the integration of copper interconnects during thefabrication of integrated circuits, comprising: preparing an inter-leveldielectric substrate; depositing a layer of Ru on the inter-leveldielectric substrate; depositing a layer of IrO₂ as a diffusion stufferon the Ru layer; and depositing copper on the IrO₂ layer.
 24. The methodof controlling and containing copper diffusion during the integration ofcopper interconnects during the fabrication of integrated circuits ofclaim 21, further comprising depositing multiple layers of Ru and IrO₂between the inter-level dielectric substrate and the copper layer.
 25. Amethod of controlling and containing copper diffusion during theintegration of copper interconnects during the fabrication of integratedcircuits, comprising: preparing an inter-level dielectric substrate;depositing one or a plurality of layers of RuO₂ on the inter-leveldielectric substrate; and depositing copper on the RuO₂ layer.
 26. Themethod of controlling and containing copper diffusion during theintegration of copper interconnects during the fabrication of integratedcircuits of claim 25, further comprising depositing the RuO₂ layer onthe inter-level dielectric using an atomic layer technique.
 27. Themethod of controlling and containing copper diffusion during theintegration of copper interconnects during fabrication of integratedcircuits of claim 25, further comprising depositing the RuO₂ layer onthe inter-level dielectric using an electrochemical technique.
 28. Themethod of controlling and containing copper diffusion during theintegration of copper interconnects during fabrication of integratedcircuits of claim 25, further comprising depositing the RuO₂ layer onthe inter-level dielectric using a thermal oxidation technique.
 29. Themethod of controlling and containing copper diffusion during theintegration of copper interconnects during fabrication of integratedcircuits of claim 25, further comprising depositing the RuO₂ layer onthe inter-level dielectric using a physical vapor technique.
 30. Amethod of controlling and containing copper diffusion during theintegration of copper interconnects during the fabrication of integratedcircuits, comprising: preparing an inter-level dielectric substrate;depositing one or a plurality of layers of Ir/Ru on the inter-leveldielectric substrate; and depositing one or a plurality of layers ofIrO₂/RuO₂ on the Ir/Ru layers; and depositing copper on the IrO₂/RuO₂layers.
 31. A method of controlling copper diffusion during theintegration of copper interconnects during integrated circuitfabrication, comprising using Ru as a diffusion barrier.
 32. The methodof controlling copper diffusion during the integration of copperinterconnects during integrated circuit fabrication of claim 31, furthercomprising eliminating a copper seed layer.
 33. A method of controllingcopper diffusion during the integration of copper interconnects duringintegrated circuit fabrication, comprising using Ru and RuO₂ as adiffusion barrier.
 34. The method of controlling copper diffusion duringthe integration of copper interconnects during integrated circuitfabrication of claim 33, further comprising eliminating a copper seedlayer.
 35. A method of controlling copper diffusion during theintegration of copper interconnects during integrated circuitfabrication, comprising using Ir as a diffusion barrier.
 36. The methodof controlling copper diffusion during the integration of copperinterconnects during integrated circuit fabrication of claim 35, furthercomprising eliminating a copper seed layer.
 37. A method of controllingcopper diffusion during the integration of copper interconnects duringintegrated circuit fabrication, comprising using Ir and IrO₂ as adiffusion barrier.
 38. The method of controlling copper diffusion duringthe integration of copper interconnects during integrated circuitfabrication of claim 37, further comprising eliminating a copper seedlayer.
 39. An integrated circuit, comprising: a plurality ofsemiconductor devices; the plurality of semiconductor devices beingcoupled via copper interconnects; the copper interconnects beingdeposited on one or a plurality of Ru layer(s); the Ru layer(s) beingdeposited on one or a plurality of RuO₂ layer(s); and the RuO₂ layer(s)being deposited on an inter-level dielectric.
 40. The integrated circuitof claim 39, further comprising the semiconductor devices and copperinterconnects having sub-micron features.
 41. An integrated circuit,comprising: a plurality of semiconductor devices; the plurality ofsemiconductor devices being coupled via copper interconnects; the copperinterconnects being deposited on one or a plurality of Ir layer(s); theIr layer(s) being deposited on one or a plurality of IrO₂ layer(s); andthe IrO₂ layer(s) being deposited on an inter-level dielectric.
 42. Theintegrated circuit of claim 41, further comprising the semiconductordevices and copper interconnects having sub-micron features.
 43. Anintegrated circuit, comprising: a plurality of semiconductor devices;the plurality of semiconductor devices being coupled via copperinterconnects; the copper interconnects being deposited on one or aplurality of Ru layer(s); the Ru layer(s) being deposited on one or aplurality of IrO₂ layer(s); and the IrO₂ layer(s) being deposited on aninter-level dielectric.
 44. The integrated circuit of claim 43, furthercomprising the semiconductor devices and copper interconnects havingsub-micron features.
 45. An integrated circuit, comprising: a pluralityof semiconductor devices; the plurality of semiconductor devices beingcoupled via copper interconnects; the copper interconnects beingdeposited on one or a plurality of Ir layer(s); the Ir layer(s) beingdeposited on one or a plurality of RuO₂ layer(s); and the RuO₂ layer(s)being deposited on an inter-level dielectric.
 46. The integrated circuitof claim 45, further comprising the semiconductor devices and copperinterconnects having sub-micron features.